arm-cortex-expert

ARM Cortex-M Embedded Development Expert Skills

Skill Overview

arm-cortex-expert is a professional ARM Cortex-M embedded systems development assistant focused on firmware and driver development, providing comprehensive technical support and code implementation solutions for platforms such as Teensy, STM32, nRF52, and SAMD.

Applicable Scenarios

1. Firmware and Driver Development

When you need to write peripheral drivers (I²C, SPI, UART, ADC, DAC, PWM, USB) for ARM Cortex-M microcontrollers, this skill can provide complete driver module implementations, including initialization code, interrupt handlers, and usage examples. Whether using HAL libraries, register-level programming, or platform-specific libraries, you can obtain reliable code implementations.

2. Advanced Performance Optimization

For performance-critical tasks such as DMA transfers, cache coherency handling, and interrupt priority configuration, this skill provides in-depth guidance on using memory barriers, DMA cache coherency solutions, and Cortex-M7-specific optimization techniques to help you avoid common timing issues and data races.

3. RTOS Integration and Concurrency

When a project requires using an RTOS like FreeRTOS or Zephyr, this skill offers best practices for interrupt-safe design, critical section management, inter-thread communication, and other concurrency patterns to ensure code safety and maintainability in a multitasking environment.

Core Features

1. Peripheral Driver Development

Provides complete implementations for peripherals such as I²C, SPI, UART, CAN, and SDIO, supporting both register-level control and HAL library wrappers. Includes interrupt-driven data pipelines, non-blocking API designs, and DMA-based high-throughput transfer schemes suitable for high-performance scenarios like audio capture and sensor data acquisition.

2. Memory Safety and Performance Optimization

Addresses the weak memory ordering characteristics of ARM Cortex-M7 and provides guidance on using memory barriers and DMA cache coherency solutions. Covers advanced topics including 32-byte-aligned DMA buffer configuration, use of non-cacheable memory such as DTCM/SRAM, and MPU region configuration.

3. Platform-Specific Support

Covers mainstream platforms including Teensy 4.x (i.MX RT1062), STM32 F4/F7/H7 series, Nordic nRF52 (BLE), and Microchip SAMD. Each platform includes targeted safety notes, clock configuration recommendations, and platform-specific API usage guides to help you avoid platform-specific pitfalls.

Frequently Asked Questions

Why does ARM Cortex-M7 need memory barriers?

ARM Cortex-M7 uses a weak memory ordering model; the CPU and hardware may reorder register read/write operations. Without memory barriers (e.g., __DMB(), __DSB()), you may encounter strange phenomena like "the program works when debug output is added but fails when it is removed" because debug output implicitly adds delays. The correct approach is to add appropriate memory barriers before and after register reads/writes to ensure the ordering of MMIO operations.

How to solve DMA cache coherency issues?

ARM Cortex-M7 devices (such as Teensy 4.x and STM32 F7/H7) have data caches, and DMA and the CPU may see different data. Solutions include: 1) using non-cacheable memory regions such as DTCM/SRAM for DMA buffers; 2) configuring the MPU to mark specific regions as non-cacheable; 3) manually performing cache clean and invalidate operations before and after DMA transfers. All DMA buffers must be 32-byte aligned and their sizes must be multiples of 32 bytes.

How to debug embedded HardFault errors?

HardFaults are usually caused by unaligned memory access (M0/M0+), null pointer dereferences, stack overflows, illegal instructions, or writes to read-only memory. On M3/M4/M7, you can check fault registers such as HFSR, CFSR, MMFAR/BFAR for detailed information. It is recommended to capture the stack frame in the HardFault handler and print/log register states to preserve the context before reset. Fault diagnosis information on M0/M0+ is limited and requires more reliance on serial output and memory inspection.

Which is better for learning embedded development, STM32 or Teensy?

Both have advantages. The STM32 ecosystem is more complete, with the STM32CubeMX graphical configuration tool, abundant official examples, and HAL library support, making it suitable for industrial application development. Teensy has a lower development barrier, is Arduino-compatible, has rich built-in USB features, and enables rapid prototyping. If the goal is to learn low-level principles, start with register-level programming; if you want fast prototyping, Teensy is a better choice.

What are the differences among ARM Cortex-M series?

M0/M0+ are entry-level, up to 50 MHz, support only the Thumb-1 instruction set, and have no FPU or cache, suitable for simple control applications. M3 adds Thumb-2 and full fault handling, up to 100 MHz. M4/M4F add DSP extensions and a single-precision FPU, up to 180 MHz. M7/M7F are the highest-performance cores, up to 600 MHz, supporting double-precision FPU, instruction and data caches, and tightly-coupled memory (TCM), suitable for high-performance applications such as audio processing and high-speed data acquisition.